Programmable logic devices (PLDs), such as field programmable gate arrays (FPGAs) or complex programmable logic devices (CPLDs), may be configured to provide user-defined features. PLDs typically include various components, such as programmable logic cells, memory cells, digital signal processing cells, input/output cells, and other components. The PLD components may be interconnected through signal paths provided by routing wires of the PLD to implement a desired circuit design.
However, PLDs typically have a limited supply of routing wires available to interconnect components from different portions of the PLD. This differs from conventional application-specific integrated circuits (ASICs) in which empty physical spaces may be reserved to implement additional signal paths at a later time if desired. Thus, if a given circuit design requires too many signals to be interconnected between certain regions of a PLD, the limited number of available wires may become nearly or completely exhausted, leading to congestion in the PLD signal paths.
Unfortunately, existing approaches to determining PLD congestion are often unsatisfactory. For example, conventional approaches to congestion estimation typically assume that signal paths will be uniformly routed throughout the available routing resources between source and destination locations of the PLD. In this regard, such approaches assume that if there are several possible signal paths between a source and destination, then all of the signal paths will be equally likely to actually be used to carry the signal from the source to destination.
As a result, such approaches may underestimate signal congestion along signal paths that are frequently selected by routing processes, and overestimate signal congestion along signal paths that less frequently selected. Accordingly, there is a need for an improved approach to estimating signal congestion in PLDs.